== Porting the RC5 Encryption Scheme to Synthesizable Verilog == [[TOC(Other/Summer/2017*, depth=4)]] === Mission === The RC5 encryption scheme (Rivest's Cypher) will be ported to an FPGA using synthesizable verilog. The benefit of this would be scalability of encryption. === Background === ==== Rivest's Cypher Encryption ==== === Progress === === Presentations === {{{ #!html Week 1

Week 2

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}}} === The Team === {{{ #!html
Nicholas Lurski
Electrical and Computer Engineering

Rutgers University


Project guided by Dr. Richard Martin.
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