== Zynq-based WISER platform - Start-up test ==

[[TOC(Tutorials/k0SDR*)]]

=== Description ===
This tutorial shows how to load the Zynq-based WISER platform (Zedboard + ADFMCOMMS1) on ORBIT and run a start-up test.

=== Hardware / Software Resources utilized ===
 1. An SB6 node with WISER platform connected to it.
 2. ''wiser_sb6_zedboard.ndz'': disk image.


=== Set up ===
 * To get started first make a reservation on the [https://www.orbit-lab.org/schedule/ Orbit Scheduler] for using the SB6.

 * After logging into SB6 console, image one of the nodes
{{{
omf load -i wiser_sb6_zedboard.ndz -t node1-1
}}}

 * Once imaging is done, turn the node on
{{{
omf tell -a on -t node1-1
}}}

 * Wait for the node to turn on and log in
{{{
ssh root@node1-1
}}}
 
=== Loading the Zedboard 
Launch XMD
{{{
root@node1-1:~# xmd
Xilinx Microprocessor Debugger (XMD) Engine
Xilinx EDK 14.7 Build EDK_P.20131013
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

XMD%
}}}

Program the FPGA with cr_top_spec_sense_rx.bit
{{{
XMD% fpga -f cr_top_spec_sense_rx.bit
Programming Bitstream -- cr_top_spec_sense_rx.bit
Fpga Programming Progress ............10.........20.........30.........40.........50.........60.........70.........80.........90........Done
Successfully downloaded bit file.

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       4ba00477           4        Cortex-A9
 2       03727093           6        XC7Z020

0
XMD%
}}}

Connect XMD to the ARM processor
{{{
XMD% connect arm hw

JTAG chain configuration
--------------------------------------------------
Device   ID Code        IR Length    Part Name
 1       4ba00477           4        Cortex-A9
 2       03727093           6        XC7Z020

--------------------------------------------------
Enabling extended memory access checks for Zynq.
Writes to reserved memory are not permitted and reads return 0.
To disable this feature, run "debugconfig -memory_access_check disable".

--------------------------------------------------

CortexA9 Processor Configuration
-------------------------------------
Version.............................0x00000003
User ID.............................0x00000000
No of PC Breakpoints................6
No of Addr/Data Watchpoints.........4

Connected to "arm" target. id = 64
Starting GDB server for "arm" target (id = 64) at TCP port no 1234
XMD%
}}}

Source ps7_init_tx_rx.tcl. This file contains initialization procedures for the ARM processor and programmable logic. Run ps7_init and ps7_post_config
{{{
XMD% source ps7_init_tx_rx.tcl
XMD% ps7_init
XMD% ps7_post_config
XMD%
}}}

=== Running a start up test