wiki:Other/Summer/2017/FPGAEncryption

Design of a pseudo-language for FPGA programming

Mission

Designing a psuedo-language based on the BASIC programming language, in order to lower the entry point for FPGA programming. The RC5 encryption scheme (Rivest's Cypher) will be ported to an FPGA using synthesizable verilog. The benefit of this would be scalability of encryption. This motive for porting the RC5 scheme using our new language is to prove the efficacy of the new language for writing FPGA programs

Presentations

Week 1

Week 2

Week 3

Week 4

Week 5

Week 7

Week 8

Week 9

The Team

Nicholas Lurski
Electrical and Computer Engineering

Rutgers University
Zarir Hamza
High School

Middlesex County Academy for Science, Mathematics and Engineering Technologies


Project guided by Dr. Richard Martin.
Last modified 8 days ago Last modified on 07/18/17 22:08:56

Attachments (8)