wiki:Other/Summer/2017/FPGAEncryption

Porting the RC5 Encryption Scheme to Synthesizable Verilog

Mission

The RC5 encryption scheme (Rivest's Cypher) will be ported to an FPGA using synthesizable verilog. The benefit of this would be scalability of encryption.

Background

Rivest's Cypher Encryption

Project Github

Progress

Presentations

Week 1

Week 2

The Team

Nicholas Lurski
Electrical and Computer Engineering

Rutgers University


Project guided by Dr. Richard Martin.
Last modified 2 weeks ago Last modified on 06/05/17 14:18:38

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